CPC H04L 9/06 (2013.01) [G06F 13/28 (2013.01); G06F 21/72 (2013.01); H04L 2209/12 (2013.01)] | 19 Claims |
1. A hardware cryptographic engine comprising:
a direct-memory-access input module for receiving input data over a memory bus; and
a cryptographic module,
wherein the cryptographic module comprises:
an input register having an input-register length; and
circuitry configured to perform a cryptographic operation on data in the input register,
wherein the hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and hardware alignment circuitry for performing an alignment operation on input data in the input-alignment buffer; and
wherein the hardware cryptographic engine is configured to pass input data, received by the direct-memory-access input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.
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