US 12,010,209 B2
Memory-efficient hardware cryptographic engine
Marko Winblad, Trondheim (NO); Markku Vähätaini, Trondheim (NO); James Nevala, Trondheim (NO); Matti Tiikkainen, Trondheim (NO); and Hannu Talvitie, Trondheim (NO)
Assigned to Nordic Semiconductor ASA, Trondheim (NO)
Appl. No. 17/059,393
Filed by Nordic Semiconductor ASA, Trondheim (NO)
PCT Filed May 29, 2019, PCT No. PCT/EP2019/064108
§ 371(c)(1), (2) Date Nov. 27, 2020,
PCT Pub. No. WO2019/229192, PCT Pub. Date Dec. 5, 2019.
Claims priority of application No. 1808834 (GB), filed on May 30, 2018.
Prior Publication US 2021/0216665 A1, Jul. 15, 2021
Int. Cl. H04L 9/06 (2006.01); G06F 13/28 (2006.01); G06F 21/72 (2013.01)
CPC H04L 9/06 (2013.01) [G06F 13/28 (2013.01); G06F 21/72 (2013.01); H04L 2209/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A hardware cryptographic engine comprising:
a direct-memory-access input module for receiving input data over a memory bus; and
a cryptographic module,
wherein the cryptographic module comprises:
an input register having an input-register length; and
circuitry configured to perform a cryptographic operation on data in the input register,
wherein the hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and hardware alignment circuitry for performing an alignment operation on input data in the input-alignment buffer; and
wherein the hardware cryptographic engine is configured to pass input data, received by the direct-memory-access input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.