CPC H04L 25/0242 (2013.01) [H04B 7/0452 (2013.01); H04B 7/0456 (2013.01); H04L 5/0051 (2013.01)] | 20 Claims |
1. A data processing apparatus, comprising:
a processor, configured to determine a computation parallelism degree according to at least one of a quantity of antennas and pilot frequency information, acquire antenna data and channel estimation matrices of respective users, store the antenna data and the channel estimation matrices in groups in a memory, and determine, according to the computation parallelism degree, target antenna data processed in parallel by an arithmetic unit in a single computation, wherein the target antenna data is part of the antenna data of the respective users;
the memory, configured to store the antenna data and the channel estimation matrices in groups, and output the target antenna data and the channel estimation matrices to the arithmetic unit; and
the arithmetic unit, configured to compute user data based on the target antenna data and the channel estimation matrices.
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