US 12,009,832 B2
Sampling switch circuits
Vlad Cretu, Maidenhead (GB); and Armin Jalili Sebardan, Maidenhead (GB)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Jun. 10, 2022, as Appl. No. 17/837,615.
Claims priority of application No. 21180467 (EP), filed on Jun. 18, 2021.
Prior Publication US 2022/0407535 A1, Dec. 22, 2022
Int. Cl. H03M 1/00 (2006.01); H03K 17/54 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/1245 (2013.01) [H03K 17/54 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A sampling switch circuit, comprising:
an input node, connected to receive an input voltage signal;
a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node;
a hold-control node connected to receive a hold-control voltage signal;
an output node connected to the drain terminal of the sampling transistor;
a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal; and
switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.