US 12,009,830 B2
Timing skew mismatch calibration for time interleaved analog to digital converters
Ankur Bal, Greater Noida (IN); and Vikram Singh, Radaur (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 6, 2022, as Appl. No. 18/075,977.
Application 18/075,977 is a continuation of application No. 17/354,126, filed on Jun. 22, 2021, granted, now 11,552,646.
Claims priority of provisional application 63/043,433, filed on Jun. 24, 2020.
Prior Publication US 2023/0101518 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/1023 (2013.01) [H03M 1/0624 (2013.01); H03M 1/0836 (2013.01); H03M 1/1215 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A time-interleaved analog to digital converter (TI-ADC), comprising:
a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal;
a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal, wherein sampling by said second sub-ADC occurs with a time skew mismatch;
a multiplexor configured to interleave the first and second digital signals to generate a third digital signal;
a processing circuit configured to generate from the first and second digital signals an error signal that estimates an error due to said time skew mismatch; and
a summation circuit configured to sum the error signal with the third digital signal to generate a digital output signal.