US 12,009,827 B2
Monitor circuitry for power management and transistor aging tracking
Kuan-Yueh Shen, Portland, OR (US); Nasser A. Kurd, Portland, OR (US); and John Fallin, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 18, 2022, as Appl. No. 17/698,844.
Application 17/698,844 is a division of application No. 16/913,933, filed on Jun. 26, 2020, granted, now 11,309,900.
Prior Publication US 2022/0209778 A1, Jun. 30, 2022
Int. Cl. H03L 7/099 (2006.01); H01R 13/66 (2006.01); H03L 7/089 (2006.01); H03L 7/189 (2006.01)
CPC H03L 7/0992 (2013.01) [H01R 13/665 (2013.01); H03L 7/0893 (2013.01); H03L 7/189 (2013.01); H01R 2201/06 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first circuit on a die; and
a delay locked loop coupled to the first circuit, the delay locked loop including a first circuit path on the die, the first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
a delay line included in the delay locked loop, the delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit;
a second circuit path included in the delay locked loop and coupled between the delay line and the second input node of the phase frequency detector; and
an analog-to-digital converter coupled to the circuit node.