CPC H03L 7/0992 (2013.01) [H01R 13/665 (2013.01); H03L 7/0893 (2013.01); H03L 7/189 (2013.01); H01R 2201/06 (2013.01)] | 11 Claims |
1. An apparatus comprising:
a first circuit on a die; and
a delay locked loop coupled to the first circuit, the delay locked loop including a first circuit path on the die, the first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
a delay line included in the delay locked loop, the delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit;
a second circuit path included in the delay locked loop and coupled between the delay line and the second input node of the phase frequency detector; and
an analog-to-digital converter coupled to the circuit node.
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