US 12,009,813 B1
Technologies for reduction of memory effects in a capacitor for qubit gate control
Sushil Subramanian, Beaverton, OR (US); Stefano Pellerano, Beaverton, OR (US); Todor Mladenov, Portland, OR (US); JongSeok Park, Hillsboro, OR (US); and Bishnu Prasad Patra, Zoetermeer (NL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 27, 2022, as Appl. No. 17/827,570.
Int. Cl. H03K 17/92 (2006.01); G06N 10/40 (2022.01); H03M 1/66 (2006.01); H10N 60/10 (2023.01)
CPC H03K 17/92 (2013.01) [G06N 10/40 (2022.01); H03M 1/66 (2013.01); H10N 60/11 (2023.02); H10N 60/128 (2023.02)] 25 Claims
OG exemplary drawing
 
1. A system comprising:
a capacitor array comprising a plurality of capacitors;
an output;
a series capacitor between the capacitor array and the output;
a plurality of switches, wherein individual switches of the plurality of switches connect a capacitor of the plurality of capacitors to the series capacitor; and
a quantum processor comprising a plurality of qubits, wherein the output is connected to the quantum processor.