US 12,009,688 B2
Charge control circuit and abnormality detection system of secondary battery
Munehiro Kozuma, Kanagawa (JP); Takayuki Ikeda, Kanagawa (JP); Takanori Matsuzaki, Kanagawa (JP); Kei Takahashi, Kanagawa (JP); Mayumi Mikami, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Appl. No. 17/283,689
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Oct. 15, 2019, PCT No. PCT/IB2019/058757
§ 371(c)(1), (2) Date Apr. 8, 2021,
PCT Pub. No. WO2020/084386, PCT Pub. Date Apr. 30, 2020.
Claims priority of application No. 2018-200636 (JP), filed on Oct. 25, 2018; and application No. 2018-200638 (JP), filed on Oct. 25, 2018.
Prior Publication US 2021/0384753 A1, Dec. 9, 2021
Int. Cl. H02J 7/00 (2006.01); G11C 11/401 (2006.01); H01L 27/06 (2006.01); H01M 10/0525 (2010.01); H01M 10/42 (2006.01); H01M 10/48 (2006.01); H01M 10/613 (2014.01); H01M 10/615 (2014.01); H01M 10/625 (2014.01); H01M 10/633 (2014.01)
CPC H02J 7/007194 (2020.01) [G11C 11/401 (2013.01); H01M 10/0525 (2013.01); H01M 10/425 (2013.01); H01M 10/4257 (2013.01); H01M 10/48 (2013.01); H01M 10/486 (2013.01); H01M 10/613 (2015.04); H01M 10/615 (2015.04); H01M 10/625 (2015.04); H01M 10/633 (2015.04); H02J 7/0029 (2013.01); H02J 7/0047 (2013.01); H01L 27/0629 (2013.01); H01M 2010/4271 (2013.01); H01M 2220/20 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A charge control circuit of a secondary battery, comprising:
a temperature sensor for sensing a temperature of the secondary battery;
a first temperature comparison circuit and a second temperature comparison circuit provided with an analog signal from the temperature sensor to generate a pulse signal;
a heating device of the secondary battery which operates in two temperature ranges set by the first temperature comparison circuit;
a cooling device of the secondary battery which operates in two temperature ranges set by the second temperature comparison circuit; and
a memory means which is configured to hold an analog signal,
wherein the memory means comprises a transistor using an oxide semiconductor for a semiconductor layer, a capacitor, a first wiring, a second wiring, and a third wiring,
wherein the transistor comprises a first gate and a second gate,
wherein a first terminal of the transistor is electrically connected to the first wiring,
wherein a second terminal of the transistor is electrically connected to a first terminal of the capacitor,
wherein the first gate of the transistor is electrically connected to the second wiring, and
wherein the second gate of the transistor is electrically connected to the third wiring.