US 12,009,575 B2
Package structure
Nan-Chin Chuang, Taipei (TW); Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); Chao-Wen Shih, Hsinchu County (TW); and Shou-Zen Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/302,003.
Application 18/302,003 is a continuation of application No. 17/351,256, filed on Jun. 18, 2021, granted, now 11,658,392.
Application 17/351,256 is a continuation of application No. 16/671,182, filed on Nov. 1, 2019, granted, now 11,043,731, issued on Jun. 22, 2021.
Application 16/671,182 is a continuation of application No. 15/879,456, filed on Jan. 25, 2018, granted, now 10,483,617, issued on Nov. 19, 2019.
Claims priority of provisional application 62/565,107, filed on Sep. 29, 2017.
Prior Publication US 2023/0261361 A1, Aug. 17, 2023
Int. Cl. H01Q 21/24 (2006.01); H01L 23/00 (2006.01); H01L 23/06 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H01Q 1/22 (2006.01); H01Q 1/52 (2006.01); H01Q 19/30 (2006.01); H01Q 21/00 (2006.01); H01Q 15/14 (2006.01); H01Q 21/28 (2006.01)
CPC H01Q 1/2283 (2013.01) [H01L 23/3107 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 24/13 (2013.01); H01Q 1/22 (2013.01); H01Q 1/52 (2013.01); H01Q 1/526 (2013.01); H01Q 19/30 (2013.01); H01Q 21/0087 (2013.01); H01Q 21/24 (2013.01); H01L 23/3128 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/18 (2013.01); H01L 2924/19102 (2013.01); H01L 2924/3025 (2013.01); H01Q 15/14 (2013.01); H01Q 21/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first redistribution circuit structure;
a semiconductor die, disposed over and electrically coupled to the first redistribution circuit structure;
a first insulating encapsulation, encapsulating the semiconductor die;
a first antenna and a second antenna, electrically coupled to the semiconductor die, wherein in a vertical projection, the first antenna and the second antenna are offset from the semiconductor die, and wherein a propagating direction of an electromagnetic wave generated from the first antenna is different from a propagating direction of an electromagnetic wave generated from the second antenna; and
a first metallic layer, disposed over the first insulating encapsulation, wherein in the vertical projection, the first metallic layer is overlapped with the semiconductor die, and wherein the first metallic layer comprises:
first signal patterns, electrically coupled to the semiconductor die; and
a first antenna ground, electrically isolated from the semiconductor die.