US 12,009,436 B2
Memory cells and integrated assemblies having charge-trapping-material with trap-enhancing-additive
Manzar Siddik, Boise, ID (US); and Terry H. Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 8, 2023, as Appl. No. 18/094,377.
Application 18/094,377 is a division of application No. 16/724,753, filed on Dec. 23, 2019, granted, now 11,569,390.
Prior Publication US 2023/0163219 A1, May 25, 2023
Int. Cl. H01L 21/00 (2006.01); G11C 16/04 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H10B 43/20 (2023.01); H10B 43/30 (2023.01)
CPC H01L 29/792 (2013.01) [G11C 16/0466 (2013.01); H01L 29/4234 (2013.01); H10B 43/20 (2023.02); H10B 43/30 (2023.02)] 24 Claims
OG exemplary drawing
 
1. A memory cell comprising a charge-trapping-region between a semiconductor channel material and a gating region, the charge-trapping-region comprising at least three charge-trapping-materials, at least two of the at least three charge-trapping-materials comprise different charge-trapping-materials; and
each of the at least two charge-trapping-materials comprising a trap-enhancing-additive.