US 12,009,434 B2
Semiconductor device including transistors and method for manufacturing the same
Hidekazu Miyairi, Kanagawa (JP); Takeshi Osada, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 19, 2023, as Appl. No. 18/098,769.
Application 18/098,769 is a continuation of application No. 17/002,971, filed on Aug. 26, 2020, granted, now 11,563,124.
Application 17/002,971 is a continuation of application No. 16/180,565, filed on Nov. 5, 2018, granted, now 10,763,372, issued on Sep. 1, 2020.
Application 16/180,565 is a continuation of application No. 15/814,919, filed on Nov. 16, 2017, granted, now 10,153,380, issued on Dec. 11, 2018.
Application 15/814,919 is a continuation of application No. 15/443,096, filed on Feb. 27, 2017, granted, now 10,170,632, issued on Jan. 1, 2019.
Application 15/443,096 is a continuation of application No. 15/071,674, filed on Mar. 16, 2016, granted, now 9,601,603, issued on Mar. 21, 2017.
Application 15/071,674 is a continuation of application No. 14/694,212, filed on Apr. 23, 2015, granted, now 9,318,512, issued on Apr. 19, 2016.
Application 14/694,212 is a continuation of application No. 13/302,222, filed on Nov. 22, 2011, granted, now 9,029,851, issued on May 12, 2015.
Application 13/302,222 is a continuation of application No. 12/581,918, filed on Oct. 20, 2009, granted, now 8,067,775, issued on Nov. 29, 2011.
Claims priority of application No. 2008-274540 (JP), filed on Oct. 24, 2008.
Prior Publication US 2023/0155033 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/4763 (2006.01); H01L 21/477 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 21/02565 (2013.01); H01L 21/47635 (2013.01); H01L 21/477 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/41733 (2013.01); H01L 29/42356 (2013.01); H01L 29/42384 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/78621 (2013.01); H01L 29/78645 (2013.01); H01L 29/78648 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor and a first wiring,
wherein the first wiring has a function of transmitting a signal which is output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor,
wherein a first conductive layer has a function of a gate of the first transistor,
wherein a second conductive layer has a function of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor,
wherein a third conductive layer has a function of a gate of the second transistor,
wherein the first conductive layer is electrically connected to the third conductive layer through the second conductive layer,
wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,
wherein the gate of the third transistor is electrically connected to a gate of the fifth transistor, and
wherein the second transistor comprises a channel formation region over and overlapping with the third conductive layer.