US 12,009,429 B2
Semiconductor device and method
Yu-Lien Huang, Jhubei (TW); Guan-Ren Wang, Hsinchu (TW); and Ching-Feng Fu, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/872,825.
Application 17/872,825 is a division of application No. 16/889,028, filed on Jun. 1, 2020, granted, now 11,888,064.
Prior Publication US 2022/0359745 A1, Nov. 10, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/823443 (2013.01); H01L 21/823821 (2013.01); H01L 29/41791 (2013.01); H01L 29/4975 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate structure over a channel region of a substrate;
a source/drain region adjacent the channel region;
a first inter-layer dielectric over the source/drain region;
a silicide between the first inter-layer dielectric and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region;
a first void exposing a surface of the silicide and the bottom surface of the source/drain region; and
a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first inter-layer dielectric, the second portion of the first source/drain contact extending through the first inter-layer dielectric and contacting the silicide.