US 12,009,422 B2
Self aligned top contact for vertical transistor
ChoongHyun Lee, Chigasaki (JP); Christopher J. Waskiewicz, Rexford, NY (US); Chanro Park, Clifton Park, NY (US); and Alexander Reznicek, Troy, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Nov. 8, 2021, as Appl. No. 17/453,874.
Prior Publication US 2023/0144407 A1, May 11, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 29/41775 (2013.01); H01L 29/66666 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region; and
a top contact partially embedded into the top source drain region
a dielectric spacer separating the metal gate from the top source drain region, wherein a width of the dielectric spacer is substantially equal to a width of the top source drain region.