US 12,009,411 B2
Forming 3D transistors using 2D Van Der Waals materials
Sheng-Kai Su, Hsinchu (TW); and Jin Cai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,377.
Application 17/874,377 is a division of application No. 16/883,271, filed on May 26, 2020.
Claims priority of provisional application 62/947,864, filed on Dec. 13, 2019.
Prior Publication US 2022/0359736 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 29/24 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric fin over a dielectric layer;
forming a ring encircling and contacting sidewalls of the dielectric fin, the ring comprising a two-dimensional semiconductor material, wherein the forming the ring comprises:
conformally depositing the two-dimensional semiconductor material; and
removing portions of the two-dimensional semiconductor material to form the ring;
forming a gate dielectric contacting top surfaces of the dielectric fin, the dielectric layer, and the two-dimensional semiconductor material;
forming a gate electrode over the gate dielectric; and
forming a source/drain contact plug contacting the two-dimensional semiconductor material.