US 12,009,408 B2
Multi-gate devices having a semiconductor layer between an inner spacer and an epitaxial feature
Wei Ju Lee, Hsinchu (TW); Chun-Fu Cheng, Hsinchu County (TW); Chung-Wei Wu, Hsin-Chu County (TW); and Zhiqiang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/870,292.
Application 17/870,292 is a division of application No. 16/931,930, filed on Jul. 17, 2020, granted, now 11,489,063.
Claims priority of provisional application 62/894,291, filed on Aug. 30, 2019.
Prior Publication US 2022/0359731 A1, Nov. 10, 2022
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01); H01L 29/0653 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
channel members vertically stacked over a substrate;
a gate structure engaging the channel members;
a gate spacer layer disposed on sidewalls of the gate structure;
an epitaxial feature abutting the channel members;
an inner spacer layer interposing the gate structure and the epitaxial feature; and
a semiconductor layer interposing the inner spacer layer and the epitaxial feature.
 
11. A semiconductor device, comprising:
one or more channel layers over a substrate;
a gate structure engaging the one or more channel layers;
a source/drain (S/D) formation assistance region partially embedded in the substrate, wherein the S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer, and wherein the isolation layer electrically isolates the semiconductor seed layer from the substrate; and
an S/D epitaxial feature connecting to the semiconductor seed layer and the one or more channel layers.
 
18. A semiconductor device, comprising:
channel members vertically stacked over a substrate;
a gate structure wrapping around each of the channel members;
an epitaxial feature abutting the channel members;
an isolation layer in physical contact with the epitaxial feature and the gate structure; and
a semiconductor layer in physical contact with the epitaxial feature and the isolation layer, wherein a top surface and a bottom surface of the semiconductor layer is covered by the isolation layer.