US 12,009,402 B2
Method of forming a gate structure in high-κ metal gate technology
Wei Cheng Wu, Zhubei (TW); Alexander Kalnitsky, San Francisco, CA (US); Shih-Hao Lo, Zhubei (TW); and Hung-Pin Ko, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 3, 2022, as Appl. No. 17/735,349.
Application 17/735,349 is a division of application No. 16/580,296, filed on Sep. 24, 2019, granted, now 11,335,786.
Claims priority of provisional application 62/799,939, filed on Feb. 1, 2019.
Prior Publication US 2022/0262914 A1, Aug. 18, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/42376 (2013.01) [H01L 29/66545 (2013.01); H01L 29/66553 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure comprising:
forming a gate dielectric structure on a substrate;
forming a sidewall spacer around the gate dielectric structure;
forming a metal structure over the gate dielectric structure;
performing an etching process on the metal structure, wherein a top surface of the metal structure is disposed below a top surface of the sidewall spacer;
forming a gate body layer over the metal structure, wherein a lower portion of the gate body layer is cupped by the metal structure, wherein a top surface of the gate body layer is vertically offset from the top surface of the metal structure;
performing a planarization process on the gate body layer until the top surface of the sidewall spacer is exposed;
converting an upper portion of the gate body layer into a silicide layer, wherein outer sidewalls of the silicide layer are aligned with outer sidewalls of the gate body layer and outer sidewalls of the metal structure; and
forming a conductive via over the metal structure, wherein the conductive via is disposed between the outer sidewalls of the gate body layer.