CPC H01L 29/42376 (2013.01) [H01L 29/66545 (2013.01); H01L 29/66553 (2013.01)] | 20 Claims |
1. A method for forming a semiconductor structure comprising:
forming a gate dielectric structure on a substrate;
forming a sidewall spacer around the gate dielectric structure;
forming a metal structure over the gate dielectric structure;
performing an etching process on the metal structure, wherein a top surface of the metal structure is disposed below a top surface of the sidewall spacer;
forming a gate body layer over the metal structure, wherein a lower portion of the gate body layer is cupped by the metal structure, wherein a top surface of the gate body layer is vertically offset from the top surface of the metal structure;
performing a planarization process on the gate body layer until the top surface of the sidewall spacer is exposed;
converting an upper portion of the gate body layer into a silicide layer, wherein outer sidewalls of the silicide layer are aligned with outer sidewalls of the gate body layer and outer sidewalls of the metal structure; and
forming a conductive via over the metal structure, wherein the conductive via is disposed between the outer sidewalls of the gate body layer.
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