CPC H01L 29/41775 (2013.01) [H01L 23/5226 (2013.01); H01L 29/401 (2013.01)] | 20 Claims |
1. A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial layer on the lower contact pattern in the contact hole;
removing a portion of the sacrificial layer to form a sacrificial pattern including a first opening;
forming a mold pattern in the first opening; and
replacing the sacrificial pattern with an upper contact pattern.
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