US 12,009,398 B2
Semiconductor devices and methods of fabricating the same
Hyun-Seung Song, Hwaseong-si (KR); Tae-Yeol Kim, Hwaseong-si (KR); and Jae-Jik Baek, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 16, 2022, as Appl. No. 17/932,851.
Application 17/932,851 is a continuation of application No. 17/034,088, filed on Sep. 28, 2020, granted, now 11,482,602.
Claims priority of application No. 10-2020-0003715 (KR), filed on Jan. 10, 2020.
Prior Publication US 2023/0011401 A1, Jan. 12, 2023
Int. Cl. H01L 29/417 (2006.01); H01L 23/522 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 23/5226 (2013.01); H01L 29/401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial layer on the lower contact pattern in the contact hole;
removing a portion of the sacrificial layer to form a sacrificial pattern including a first opening;
forming a mold pattern in the first opening; and
replacing the sacrificial pattern with an upper contact pattern.