US 12,009,394 B2
Source/drain contacts and methods of forming same
Li-Zhen Yu, New Taipei (TW); Huan-Chieh Su, Tianzhong Township (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 19, 2022, as Appl. No. 18/083,792.
Application 18/083,792 is a continuation of application No. 17/091,159, filed on Nov. 6, 2020, granted, now 11,532,713.
Claims priority of provisional application 63/044,129, filed on Jun. 25, 2020.
Prior Publication US 2023/0120499 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/41733 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02603 (2013.01); H01L 23/5286 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a device layer comprising a first transistor;
a first interconnect structure on a front-side of the device layer; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a gate stack of the first transistor; and
a source/drain contact extending through the first dielectric layer to a source/drain region of the first transistor, wherein the source/drain contact electrically connects the source/drain region to a power rail in the second interconnect structure.