US 12,009,389 B2
Edge termination for power semiconductor devices and related fabrication methods
Woongsun Kim, Cary, NC (US); Daniel Jenner Lichtenwalner, Raleigh, NC (US); Sei-Hyung Ryu, Cary, NC (US); and Naeem Islam, Morrisville, NC (US)
Assigned to WOLFSPEED, INC., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Nov. 30, 2021, as Appl. No. 17/538,026.
Prior Publication US 2023/0170383 A1, Jun. 1, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0619 (2013.01) [H01L 29/66712 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A power semiconductor device, comprising:
a semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type,
wherein one or more of the guard rings extend in the semiconductor drift region to a depth of greater than about 1 micrometers (μm) relative to a surface of the semiconductor layer structure, and two or more of the guard rings are laterally separated from one another by a spacing of less than about 3 μm.