US 12,009,387 B2
Integrated circuit device and method of manufacturing the same
Jun-goo Kang, Seoul (KR); Hyun-suk Lee, Suwon-si (KR); and Gi-hee Cho, Yongin-si (KR)
Assigned to Samsung Electronics, Co. Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 18, 2021, as Appl. No. 17/323,433.
Application 17/323,433 is a continuation of application No. 16/555,210, filed on Aug. 29, 2019, granted, now 11,031,460.
Claims priority of application No. 10-2019-0020057 (KR), filed on Feb. 20, 2019.
Prior Publication US 2021/0273041 A1, Sep. 2, 2021
Int. Cl. H10B 12/00 (2023.01); H01L 49/02 (2006.01)
CPC H01L 28/75 (2013.01) [H01L 28/60 (2013.01); H01L 28/87 (2013.01); H01L 28/88 (2013.01); H01L 28/90 (2013.01); H10B 12/0335 (2023.02); H10B 12/31 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a substrate;
an insulating interlayer on the substrate;
an etch stop layer on the insulating interlayer;
a lower electrode structure disposed over the insulating interlayer;
a dielectric layer disposed on the lower electrode structure; and
an upper electrode disposed on the dielectric layer,
wherein the lower electrode structure includes a first lower electrode, a second lower electrode that is disposed on the first lower electrode, and a third lower electrode that is disposed on the second lower electrode,
a bottom surface of the second lower electrode of the lower electrode structure contacts a top surface of the first lower electrode of the lower electrode structure,
the dielectric layer contacts the first lower electrode, the second lower electrode and the third lower electrode of the lower electrode structure, and
an outer bottommost point of the dielectric layer is below a topmost surface of the insulating interlayer.