US 12,009,381 B2
Solid-state imaging device
Hironobu Fukui, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/595,529
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed May 27, 2020, PCT No. PCT/JP2020/020997
§ 371(c)(1), (2) Date Nov. 18, 2021,
PCT Pub. No. WO2020/241717, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 2019-102044 (JP), filed on May 31, 2019.
Prior Publication US 2022/0271069 A1, Aug. 25, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01)
CPC H01L 27/1463 (2013.01) [H01L 27/14612 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01)] 14 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a first semiconductor substrate comprising a plurality of unit regions and a potential adjustment region;
a photoelectric converter for each of the plurality of unit regions;
an isolation region that runs through the first semiconductor substrate in a thickness direction of the first semiconductor substrate and is configured to electrically isolate the plurality of unit regions from each other;
a charge holding section that is electrically coupled to the photoelectric converter and configured to receive signal charge from the photoelectric converter; and
a charge accumulation section that is shared by at least two unit regions of the plurality of unit regions and to which the signal charge is transferred from the photoelectric converter, wherein
the charge holding section of each of the plurality of unit regions shares the charge accumulation section, and
a potential barrier between the photoelectric converter and the charge holding section is adjusted to be smaller than a potential barrier between the photoelectric converter and the charge accumulation section based on the potential adjustment region.