US 12,009,344 B2
Semiconductor package including stacked semiconductor chips
Jin Kyoung Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 12, 2021, as Appl. No. 17/200,063.
Claims priority of application No. 10-2020-0176399 (KR), filed on Dec. 16, 2020.
Prior Publication US 2022/0189924 A1, Jun. 16, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/48 (2013.01); H01L 2224/48147 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a base layer;
a chip stack stacked over the base layer, the chip stack includes first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include chip identification pads;
inter-chip wires connecting the chip identification pads of one semiconductor chip of the chip stack with the chip identification pads of adjacent semiconductor chip of the chip stack; and
stack wires connecting the chip identification pads of the first semiconductor chip to the base layer,
wherein the chip identification pads include first and second chip identification pads,
wherein each of the first and second chip identification pads of the first semiconductor chip are connected to the base layer via the stack wires,
wherein the inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein the inter-chip wires are configured to supply power to the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
wherein the inter-chip wires are configured to supply power to the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
wherein the inter-chip wires are configured to supply power to the third semiconductor chip through the second chip identification pad of the third semiconductor chip.
 
6. A semiconductor package comprising:
a base layer;
a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to eighth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads;
first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack;
first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer;
second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack; and
second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer,
wherein the chip identification pads include first to third chip identification pads,
wherein the first, second, and third chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires, respectively,
wherein, in the first chip stack, the first inter-chip wires connect to two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other,
wherein the first, second, and third chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires, respectively,
wherein, in the second chip stack, the second inter-chip wires connect two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other.
 
11. A semiconductor package comprising:
a base layer;
a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads;
first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack;
first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer;
second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack;
second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer,
wherein the chip identification pads include first and second chip identification pads,
wherein each of the first and second chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires,
wherein, in the first chip stack, the first inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein each of the first and second chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires,
wherein, in the second chip stack, the second inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein, in the first chip stack, the first inter-chip wires are configured to supply power to:
the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
the third semiconductor chip through the second chip identification pad of the third semiconductor chip.