US 12,009,333 B2
Semiconductor device
Satoshi Shiraki, Nagano (JP)
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed by SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed on Dec. 23, 2021, as Appl. No. 17/645,815.
Application 17/645,815 is a division of application No. 16/510,087, filed on Jul. 12, 2019, granted, now 11,239,196.
Claims priority of application No. 2018-147942 (JP), filed on Aug. 6, 2018.
Prior Publication US 2022/0115353 A1, Apr. 14, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/495 (2006.01); H01L 23/532 (2006.01)
CPC H01L 24/32 (2013.01) [H01L 23/49513 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 23/49586 (2013.01); H01L 23/5329 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 23/053 (2013.01); H01L 23/49503 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a chip mounting member; and
a semiconductor chip bonded to the chip mounting member through a metal sintered material,
wherein the metal sintered material includes a first portion exactly overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the first portion in the plan view, the first portion and the second portion being arranged next to each other without a gap therebetween,
wherein a porosity ratio of the first portion is lower than a porosity ratio of the second portion, and
wherein a thickness of the first portion is less than a thickness of any part of the second portion.