US 12,009,318 B2
Control of warpage using ABF GC cavity for embedded die package
Digvijay A. Raorane, Chandler, AZ (US); Ian En Yoon Chin, Georgetown (MY); and Daniel N. Sobieski, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 6, 2022, as Appl. No. 17/714,944.
Application 15/948,958 is a division of application No. 14/491,892, filed on Sep. 19, 2014, granted, now 9,941,219, issued on Apr. 10, 2018.
Application 17/714,944 is a continuation of application No. 16/849,707, filed on Apr. 15, 2020, granted, now 11,322,457.
Application 16/849,707 is a continuation of application No. 15/948,958, filed on Apr. 9, 2018, granted, now 10,658,307, issued on May 19, 2020.
Prior Publication US 2022/0230972 A1, Jul. 21, 2022
Int. Cl. H01L 23/49 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/50 (2013.01); H01L 23/498 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 23/3121 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall;
a plurality of conductive contacts at the second side of the die; a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die;
a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts;
a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts;
a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via;
a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die.