US 12,009,295 B2
Comb / fishbone metal stack
Thomas Hua-Min Williams, Irvine, CA (US); Matthew Chauncey Kusbit, Santee, CA (US); Luis Chen, Chula Vista, CA (US); Keyurkumar Karsanbhai Kansagra, Bangalore (IN); and Smeeta Heggond, Bagalkot (IN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 9, 2021, as Appl. No. 17/454,203.
Prior Publication US 2023/0141245 A1, May 11, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 27/092 (2013.01)] 46 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a first set of metal oxide semiconductor (MOS) transistors, the first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B;
a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A, each interconnect stack of the first plurality of interconnect stacks extending in a second direction over at least a portion of the first set of MOS transistors and including consecutive metal layer interconnects; and
a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks, the first comb interconnect structure being coupled to the first plurality of interconnect stacks, wherein
each interconnect stack of the first plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the first plurality of interconnect stacks, wherein i=1 and q>=4, and the first comb interconnect structure is on a metal q (Mq) layer.