US 12,009,294 B2
Middle-of-line interconnect structure and manufacturing method
Cheng-Wei Chang, Taipei (TW); Sung-Li Wang, Zhubei (TW); Yi-Ying Liu, Hsinchu (TW); Chia-Hung Chu, Taipei (TW); and Fang-Wei Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/875,533.
Application 17/875,533 is a division of application No. 16/844,133, filed on Apr. 9, 2020, granted, now 11,462,471.
Claims priority of provisional application 62/908,029, filed on Sep. 30, 2019.
Prior Publication US 2022/0367348 A1, Nov. 17, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/28568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76864 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, comprising:
forming a lower inter-layer dielectric (ILD) layer over a substrate;
forming a lower conductive plug through the lower ILD layer on a source/drain region of a transistor structure;
forming a capping layer on the lower conductive plug;
forming an upper ILD layer over the lower ILD layer and the capping layer; and
forming an upper conductive plug through the upper ILD layer reaching the capping layer;
wherein the upper conductive plug is formed by forming a metal core followed by an annealing process to form an intermixing barrier layer lining an interface of the metal core and the upper ILD layer.