US 12,009,293 B2
Barrier-free interconnect structure and manufacturing method thereof
Pei-Yu Wang, Hsinchu (TW); Cheng-Ting Chung, Hsinchu (TW); and Wei Ju Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 14, 2022, as Appl. No. 17/693,925.
Application 17/693,925 is a division of application No. 16/572,670, filed on Sep. 17, 2019, granted, now 11,276,637.
Prior Publication US 2022/0199523 A1, Jun. 23, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/7685 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first dielectric layer over a contact feature using flowable chemical vapor deposition (FCVD) or spin-on coating, the first dielectric layer comprising a first top surface;
forming a contact via extending through the first dielectric layer and having a second top surface above the first top surface of the first dielectric layer;
depositing a barrier layer over the first dielectric layer and the contact via;
planarizing the barrier layer by chemical mechanical polishing to expose the first top surface of the contact via while the first dielectric layer remains covered by the barrier layer; and
after the planarizing, patterning the barrier layer to form a patterned barrier layer and expose a portion of the first dielectric layer.