US 12,009,289 B2
Semiconductor package and manufacturing method thereof
Jae Ung Lee, Seoul (KR); Yung Woo Lee, Anyang-si (KR); EunNaRa Cho, Seoul (KR); Dong Hyun Bang, Seoul (KR); Wook Choi, Seoul (KR); KooWoong Jeong, Seoul (KR); Byong Jin Kim, Bucheon-si (KR); Min Chul Shin, Bucheon-si (KR); Ho Jeong Lim, Bucheon-si (KR); Ji Hyun Kim, Seoul (KR); and Chang Hun Kim, Seoul (KR)
Assigned to Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte Ltd., Singapore (SG)
Filed on Oct. 14, 2021, as Appl. No. 17/501,857.
Application 17/501,857 is a continuation of application No. 16/042,798, filed on Jul. 23, 2018, granted, now 11,152,296.
Application 16/042,798 is a continuation of application No. 15/149,141, filed on May 8, 2016, granted, now 10,032,705, issued on Jul. 24, 2018.
Claims priority of application No. 10-2015-0099070 (KR), filed on Jul. 13, 2015.
Prior Publication US 2022/0051973 A1, Feb. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/50 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/13 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 25/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15159 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/19106 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate comprising:
a first substrate surface;
a second substrate surface opposite the first substrate surface;
a recess portion in the first substrate surface and extending toward the second substrate surface;
a plurality of recess conductive patterns in the recess portion;
a dielectric layer having a first dielectric surface, a second dielectric surface, and a side dielectric surface extending between the first dielectric surface and the second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface adjacent the side dielectric surface;
a first conductive pattern at the first dielectric surface;
a second conductive pattern at the second dielectric surface; and
a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern;
a passive element positioned in the recess portion of the substrate and comprising a first electrode and a second electrode, each electrically connected to a respective pattern of the plurality of recess conductive patterns;
a semiconductor die mounted on the first dielectric surface and connected to the first conductive pattern;
a layer of a single continuous encapsulating material that contacts the side dielectric surface, covers at least a first side and lateral sides of the passive element, covers at least a portion of the first substrate surface, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer.