US 12,009,288 B2
Interconnection structure and semiconductor package including the same
Dongjoon Oh, Suwon-si (KR); Junyun Kweon, Cheonan-si (KR); Jumyong Park, Cheonan-si (KR); Jin Ho An, Seoul (KR); Chungsun Lee, Asan-si (KR); and Hyunsu Hwang, Siheung-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 14, 2021, as Appl. No. 17/230,511.
Claims priority of application No. 10-2020-0106056 (KR), filed on Aug. 24, 2020.
Prior Publication US 2022/0059442 A1, Feb. 24, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 23/3128 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An interconnection structure, comprising:
a first dielectric layer and a first hardmask pattern that are sequentially stacked; and
a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer, wherein
the first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer,
the first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other,
the first pad part vertically overlapping the via part,
the line part extends from the first pad part,
a level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part,
a top surface of the first pad part and a top surface of the line part are coplanar with a top surface of the first hardmask pattern, and
the bottom surface of the first pad part, the bottom surface of the line part, and a lateral surface of the via part are in contact with the first dielectric layer.