US 12,009,277 B2
Semiconductor package
Dong Kyu Kim, Anyang-si (KR); Jung-Ho Park, Cheonan-si (KR); Jong Youn Kim, Seoul (KR); Yeon Ho Jang, Goyang-si (KR); and Jae Gwon Jang, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 18, 2022, as Appl. No. 17/866,866.
Application 17/866,866 is a continuation of application No. 16/743,284, filed on Jan. 15, 2020, granted, now 11,404,346.
Claims priority of application No. 10-2019-0077851 (KR), filed on Jun. 28, 2019.
Prior Publication US 2022/0352050 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/3675 (2013.01) [H01L 21/4871 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2221/68331 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor chip and a second semiconductor chip on a substrate, the first and second semiconductor chips being equal in thickness such that uppermost faces of the first and second semiconductor chips are located at a same height from the substrate;
a barrier layer having an opening that exposes a first portion of the uppermost face of the first semiconductor chip, the barrier layer being in contact with a second portion of the uppermost face of the first semiconductor chip not exposed by the opening and an entirety of the uppermost face of the second semiconductor chip and; and
a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.