US 12,009,269 B2
Virtual metrology for feature profile prediction in the production of memory devices
Cheng-Chung Chu, Milpitas, CA (US); Masaaki Higashitani, Cupertino, CA (US); Yusuke Ikawa, Yokohama (JP); Seyyed Ehsan Esfahani Rashidi, San Jose, CA (US); Kei Samura, Yokohama (JP); Tsuyoshi Sendoda, Kuwana (JP); and Yanli Zhang, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Apr. 21, 2022, as Appl. No. 17/725,695.
Application 17/725,695 is a continuation in part of application No. 17/360,573, filed on Jun. 28, 2021.
Prior Publication US 2022/0415718 A1, Dec. 29, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 27/11578 (2017.01); H10B 43/20 (2023.01); H10B 43/10 (2023.01)
CPC H01L 22/14 (2013.01) [H01L 22/12 (2013.01); H01L 22/26 (2013.01); H10B 43/20 (2023.02); H10B 43/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first plurality of an integrated circuit as first test samples, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
performing one or more first tests on the first test samples to determine a corresponding one or more metrology data values for each of the first test samples;
performing one or more second tests on the first plurality of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
performing a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
receiving a second plurality of the integrated circuit;
determining, for the second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers; and
interpolating metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers.