US 12,009,268 B2
Semiconductor device and fabrication method for semiconductor device
Motoyoshi Kubouchi, Matsumoto (JP); Kosuke Yoshida, Matsumoto (JP); Soichi Yoshida, Matsumoto (JP); Koh Yoshikawa, Matsumoto (JP); and Nao Suganuma, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Jul. 14, 2023, as Appl. No. 18/352,285.
Application 17/902,921 is a division of application No. 16/899,523, filed on Jun. 11, 2020, granted, now 11,450,734, issued on Sep. 20, 2022.
Application 18/352,285 is a continuation of application No. 17/902,921, filed on Sep. 5, 2022, granted, now 11,742,249.
Claims priority of application No. 2019-111761 (JP), filed on Jun. 17, 2019; application No. 2020-006044 (JP), filed on Jan. 17, 2020; and application No. 2020-087040 (JP), filed on May 18, 2020.
Prior Publication US 2023/0369137 A1, Nov. 16, 2023
Int. Cl. H01L 29/739 (2006.01); H01L 21/22 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/66 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/32 (2006.01); H01L 29/40 (2006.01); H01L 29/861 (2006.01)
CPC H01L 22/12 (2013.01) [H01L 21/221 (2013.01); H01L 21/265 (2013.01); H01L 21/26526 (2013.01); H01L 21/324 (2013.01); H01L 27/0664 (2013.01); H01L 29/0611 (2013.01); H01L 29/0615 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/32 (2013.01); H01L 29/407 (2013.01); H01L 29/7397 (2013.01); H01L 29/8613 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate;
a first lower surface region of a first conductivity type provided in at least a part of a lower surface of the semiconductor substrate;
a base region of a second conductivity type provided on the upper surface side of the semiconductor substrate;
a first region of the first conductivity type provided in the semiconductor substrate and disposed between the base region and the first lower surface region in a depth direction of the semiconductor substrate;
a first upper surface region of the first conductivity type provided on an upper surface of the semiconductor substrate; and
a first bottom region of the second conductivity type provided in the semiconductor substrate and disposed continuously in the first direction such that the first bottom region is in contact with bottom portions of the plurality of trench portions, wherein
in a cross section that (i) is along the first direction and perpendicular to the upper surface and the lower surface of the semiconductor substrate and (ii) passes through the first lower surface region, one end portion of the first bottom region in the first direction locates directly above the first lower surface region in the depth direction.