US 12,009,259 B2
Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof
Sheng-Tsung Wang, Hsinchu (TW); Chia-Hao Chang, Hsinchu (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/460,405.
Prior Publication US 2023/0066705 A1, Mar. 2, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
depositing a sacrificial metal contact etch stop layer (M-CESL) over a first interlayer dielectric layer (ILD) having a source/drain metal contact formed therein, wherein an isolation feature is formed above the source/drain metal contact;
depositing a second ILD layer over the sacrificial M-CESL layer;
forming a contact opening by patterning the second ILD layer and the sacrificial M-CESL layer;
filling the contact opening with a conductive material;
performing a planarization process to remove the second ILD layer and the conductive material in the second ILD layer to expose the sacrificial M-CESL layer;
removing the sacrificial M-CESL layer; and
depositing a low-k dielectric layer to cover the conductive material.