US 12,009,257 B2
Semiconductor device
Chia-Hao Chang, Hsinchu (TW); Jia-Chuan You, Taoyuan (TW); Yu-Ming Lin, Hsinchu (TW); Chih-Hao Wang, Hsinchu County (TW); and Wai-Yi Lien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/874,170.
Application 16/871,983 is a division of application No. 15/719,395, filed on Sep. 28, 2017, granted, now 10,651,085, issued on May 12, 2020.
Application 17/874,170 is a continuation of application No. 16/871,983, filed on May 11, 2020, granted, now 11,404,315.
Prior Publication US 2022/0367268 A1, Nov. 17, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01)
CPC H01L 21/76895 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a channel region and a source/drain region;
a gate electrode over the channel region;
a source/drain contact over the source/drain region;
a conductive structure over a top surface of the source/drain contact;
an interlayer dielectric (ILD) layer surrounding the conductive structure and over the gate electrode;
an etch stop layer over the conductive structure and the ILD layer, wherein the etch stop layer comprises a material different from that of the ILD layer, and a top surface of the conductive structure is in contact with a bottom surface of the etch stop layer;
a dielectric liner at a sidewall of the conductive structure, wherein the dielectric liner extends from the top surface of the source/drain contact to the bottom surface of the etch stop layer; and
a gate contact over the gate electrode, wherein a top surface of the gate contact is higher than a top surface of the etch stop layer.