US 12,009,253 B2
Semiconductor structure with staggered selective growth
Zhi-Chang Lin, Hsinchu County (TW); Teng-Chun Tsai, Hsinchu (TW); and Wei-Hao Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 16, 2020, as Appl. No. 17/099,564.
Application 17/099,564 is a continuation of application No. 16/366,984, filed on Mar. 27, 2019, granted, now 10,840,133.
Claims priority of provisional application 62/737,279, filed on Sep. 27, 2018.
Prior Publication US 2021/0090944 A1, Mar. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/76835 (2013.01) [H01L 21/0228 (2013.01); H01L 21/02304 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 21/823475 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01); H01L 29/4232 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate;
a first via feature and a second via feature disposed on the semiconductor substrate; and
a staggered dielectric feature interposed between the first and second via features, wherein
the staggered dielectric feature includes a plurality of first dielectric layers and a plurality of second dielectric layers being interdigitated,
the first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material, and
each of the first dielectric layers and each of the second dielectric layers continuously extends from the first via feature to the second via feature, and contacts both the first and second via features.