US 12,009,209 B2
Process for preparing a support for a semiconductor structure
Young-Pil Kim, Grenoble (FR)
Assigned to Soitec, Bernin (FR)
Filed by Soitec, Bernin (FR)
Filed on Oct. 6, 2022, as Appl. No. 17/938,427.
Application 17/938,427 is a continuation of application No. 16/618,757, granted, now 11,508,578, previously published as PCT/EP2018/067262, filed on Jun. 27, 2018.
Claims priority of application No. 1756092 (FR), filed on Jun. 30, 2017.
Prior Publication US 2023/0033356 A1, Feb. 2, 2023
Int. Cl. H01L 21/02 (2006.01); C23C 16/24 (2006.01); C23C 16/26 (2006.01); C23C 16/44 (2006.01)
CPC H01L 21/02658 (2013.01) [C23C 16/24 (2013.01); C23C 16/26 (2013.01); C23C 16/4404 (2013.01); C23C 16/4405 (2013.01); H01L 21/02238 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A charge trapping layer for a semiconductor structure support, comprising:
at least one polycrystalline charge trapping material; and
at least one polycrystalline interlayer directly adjacent to the charge trapping material, the at least one polycrystalline interlayer comprising an alloy of silicon and carbon,
wherein a lattice parameter of the at least one polycrystalline charge trapping material is greater than a lattice parameter of the at least one polycrystalline interlayer.