US 12,009,058 B2
Address latch, address control circuit and semiconductor apparatus including the address control circuit
Ji Eun Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 15, 2022, as Appl. No. 17/672,069.
Claims priority of application No. 10-2021-0119099 (KR), filed on Sep. 7, 2021.
Prior Publication US 2023/0071572 A1, Mar. 9, 2023
Int. Cl. G11C 8/00 (2006.01); G06F 3/06 (2006.01); G11C 8/06 (2006.01); G11C 8/10 (2006.01)
CPC G11C 8/06 (2013.01) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 8/10 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An address latch comprising:
a first address processing unit configured to latch external address signals to output first latched signals through an output node based on a read command and a write command; and
a second address processing unit configured to latch the external address signals based on the read command with a burst length that is set to a first value and configured to output second latched signals through the output node based on an internal read command.