US 12,009,057 B2
Semiconductor memory device and memory system including the same
Hojun Yoon, Suwon-si (KR); Youngchul Cho, Suwon-si (KR); Youngdon Choi, Suwon-si (KR); Changsik Yoo, Suwon-si (KR); and Junghwan Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 5, 2023, as Appl. No. 18/143,967.
Application 18/143,967 is a continuation of application No. 17/526,398, filed on Nov. 15, 2021, granted, now 11,699,472.
Claims priority of application No. 10-2021-0051584 (KR), filed on Apr. 21, 2021.
Prior Publication US 2023/0307022 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a quadrature error correction circuit configured to perform a relocking operation to lock a second corrected clock signal to a first corrected clock signal in response to a relock signal in a second operation mode, wherein the first corrected clock signal and the second corrected clock signal have a phase difference of 90 degrees with respect to each other and are generated based on first through fourth clock signals in a first operation mode;
a clock generation circuit configured to generate an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal; and
a data input/output (I/O) buffer configured to generate a data signal by sampling data from a memory cell array based on the output clock signal and configured to transmit the data signal and the strobe signal to an external memory controller.