US 12,009,049 B2
Non-volatile memory with shared data transfer latches
Hua-Ling Cynthia Hsu, Fremont, CA (US); YenLung Li, San Jose, CA (US); Siddarth Naga Murty Bassa, San Jose, CA (US); and Jeongduk Sohn, San Ramon, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Aug. 31, 2022, as Appl. No. 17/900,066.
Prior Publication US 2024/0071433 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1057 (2013.01) [G11C 7/1048 (2013.01); G11C 2207/101 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a control circuit configured to connect to an array of non-volatile memory cells, the control circuit comprising:
a first plurality of data latches configured to connect to non-volatile memory cells of a first plane;
a second plurality of data latches configured to connect to non-volatile memory cells of a second plane; and
a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.