| CPC G11C 5/148 (2013.01) [G11C 8/10 (2013.01); G11C 8/18 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a first power supply unit configured to:
during a normal mode of a high frequency operation, supply a first power from a first global power rail to a third global power rail and to a fourth global power rail,
during a standby mode of the high frequency operation, supply the first power to the third global power rail and not supply the first power to the fourth global power rail,
during a normal mode of a low frequency operation, supply a second power from a second global power rail to the third global power rail and the fourth global power rail, and
during a standby mode of the low frequency operation, supply the second power to the third global power rail and not supply the second power to the fourth global power rail; and
a second power supply unit configured to:
during both the normal mode of the high frequency operation and the normal mode of the low frequency operation, supply a first internal power from the third global power rail to a plurality of first local power rails and to supply a second internal power from the fourth global power rail to a plurality of second local power rails, and
during both the standby mode of the high frequency operation and the standby mode of the low frequency operation, not supply the first internal power to the plurality of first local power rails and not supply the second internal power to the plurality of second local power rails,
wherein a level of the first power is greater than that of the second power.
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