US 12,009,045 B2
Management of multiple memory in-field self-repair options
Devanathan Varadarajan, Allen, TX (US); and Varun Singh, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 17, 2022, as Appl. No. 17/843,897.
Application 17/843,897 is a continuation of application No. 16/539,805, filed on Aug. 13, 2019, granted, now 11,373,726.
Claims priority of provisional application 62/828,543, filed on Apr. 3, 2019.
Prior Publication US 2022/0319627 A1, Oct. 6, 2022
Int. Cl. G11C 29/44 (2006.01); G11C 17/16 (2006.01); G11C 29/14 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 17/16 (2013.01); G11C 29/14 (2013.01); G11C 29/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a memory; and
a memory repair circuit coupled to the memory, comprising:
a first repair circuit configured to repair an error in the memory using an error correcting code; and
a second repair circuit configured to repair an error in the memory using a redundant portion of the memory,
wherein the memory repair circuit is configured to:
receive stored test data from the memory;
determine an error in the memory based on the stored test data;
select one of the first repair circuit and the second repair circuit based on enablement of the first repair circuit and the second repair circuit; and
repair the determined error in the memory with the selected repair circuit.