US 12,009,044 B2
Memory built-in self-test with automated multiple step reference trimming
Jongsin Yun, Portland, OR (US); and Martin Keim, Sherwood, OR (US)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Appl. No. 17/757,013
Filed by Siemens Industry Software Inc., Plano, TX (US)
PCT Filed Aug. 28, 2020, PCT No. PCT/US2020/048341
§ 371(c)(1), (2) Date Jun. 8, 2022,
PCT Pub. No. WO2021/118658, PCT Pub. Date Jun. 17, 2021.
Claims priority of provisional application 62/945,457, filed on Dec. 9, 2019.
Prior Publication US 2023/0049928 A1, Feb. 16, 2023
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/4401 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device configured to sense values of stored data using a reference trim during memory read operations; and
a memory built-in self-test system configured to prompt the memory device to perform a plurality of the memory read operations with different locations for a range of available values of the reference trim relative to read characteristics of the memory device and with multiple values for the reference trim with the range, wherein the memory built-in self-test system is configured to set a location for the range of available values of the reference trim relative to the read characteristics of the memory device based, at least in part, on failures of the memory device to correctly sense the stored data during the memory read operations with the different locations for the range of available values of the reference trim, and wherein the memory built-in self-test system is further configured to set the reference trim for the memory device within the range of available values of the reference trim.