US 12,009,024 B2
Circuit for reading out data, method for reading out data and memory
Xianjun Wu, Hefei (CN); and Weibing Shang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 2, 2022, as Appl. No. 17/810,596.
Application 17/810,596 is a continuation of application No. PCT/CN2022/088719, filed on Apr. 24, 2022.
Claims priority of application No. 202210203723.6 (CN), filed on Mar. 3, 2022.
Prior Publication US 2023/0282268 A1, Sep. 7, 2023
Int. Cl. G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit for reading out data, applicable for a memory, wherein the memory comprises a read-write control circuit, a column decoding circuit and a plurality of storage areas, and the circuit comprises:
a delay generation circuit, configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and a data transmission delay time of each of the storage areas, and generate a grab enable signal based on all sub-grab signals,
wherein the data transmission delay time of the storage area close to the column decoding circuit is less than the data transmission delay time of the storage area far from the column decoding circuit,
a time interval between a time when the read-write control circuit receives data transmitted from a global data line by each of the storage areas and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range;
the read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal; and
the global data line is configured to read out data of the storage areas through the column decoding circuit based on a column selection signal.