US 12,009,023 B2
Training for chip select signal read operations by memory devices
Zhenglong Wu, Shanghai (CN); Tonia G. Morris, Wendell, NC (US); Christina Jue, Cedar Park, TX (US); Daniel Becerra Perez, Zapopan (MX); and David G. Ellis, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/441,667
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed May 24, 2019, PCT No. PCT/CN2019/088263
§ 371(c)(1), (2) Date Sep. 21, 2021,
PCT Pub. No. WO2020/237410, PCT Pub. Date Dec. 3, 2020.
Prior Publication US 2022/0148639 A1, May 12, 2022
Int. Cl. G11C 11/4076 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A host system comprising:
a processor; and
a memory controller coupled to the processor, the memory controller to:
request a first reference voltage to be applied by memory devices;
during use of the first reference voltage by the memory devices:
transmit, to the memory devices, a chip select (CS) signal after various delay amounts and
receive, from the memory devices, samples of the CS signal transmitted after the various delay amounts;
request a second reference voltage to be applied by the memory devices;
during use of the second reference voltage by the memory devices:
transmit, to the memory devices, the CS signal after various delay amounts; and
receive, from the memory devices, samples of the CS signal transmitted after the various delay amounts, wherein the processor is to determine a reference voltage for the memory devices based on the first and second reference voltages that provides a composite eye width that is closest to a reference eye width and determine a delay to transmit a subsequent CS signal based on the composite eye width.