US 12,009,020 B2
Memory device generating optimal write voltage based on size of memory cell and initial write voltage
Daeshik Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 29, 2022, as Appl. No. 17/707,027.
Claims priority of application No. 10-2021-0049954 (KR), filed on Apr. 16, 2021.
Prior Publication US 2022/0336000 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01); H10B 61/20 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a first memory cell region and a second memory cell region;
a voltage generator configured to generate a code corresponding to a write voltage; and
a write driver configured to store data in the first memory cell region in response to the code,
wherein the second memory cell region stores a value defining the write voltage, and
the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.