US 12,008,957 B2
Pixel compensation circuit, display panel and display device
Liuqi Zhang, Shenzhen (CN)
Assigned to Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/431,157
Filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
PCT Filed Jun. 9, 2021, PCT No. PCT/CN2021/099086
§ 371(c)(1), (2) Date Aug. 14, 2021,
PCT Pub. No. WO2022/252267, PCT Pub. Date Dec. 8, 2022.
Claims priority of application No. 202110599732.7 (CN), filed on May 31, 2021.
Prior Publication US 2024/0013716 A1, Jan. 11, 2024
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A pixel compensation circuit, comprising: a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor;
wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source;
wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node;
wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node;
wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node; and
wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node;
wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on;
wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off;
wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off;
wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off;
wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off; and
wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off.