CPC G06F 9/3887 (2013.01) [G06F 9/30098 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a graphics processor that includes:
first storage circuitry configured to store multiple thread-specific versions of a first register for a threads of a single-instruction multiple-data (SIMD) group;
second storage circuitry configured to store multiple thread-specific versions of a second register for the threads of the SIMD group;
third storage circuitry configured to store multiple thread-specific versions of a third register for threads of the SIMD group; and
a set of multiple hardware pipelines configured to:
execute, using routing circuitry, an instruction to:
store a proper subset of the thread-specific versions of the first register from the first storage circuitry in thread-specific versions of the third register in the third storage circuitry; and
store a proper subset of the thread-specific versions of the second register from the second storage circuitry in thread-specific versions of the third register in the third storage circuitry;
wherein the storage of the proper subsets stores values that are based on thread-specific versions of the first and second registers to other threads' versions of the third register for the SIMD group.
|