US 12,008,377 B2
SIMD operand permutation with selection from among multiple registers
Christopher A. Burns, Austin, TX (US); Liang-Kai Wang, Austin, TX (US); Robert D. Kenney, Austin, TX (US); and Terence M. Potter, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 12, 2023, as Appl. No. 18/299,452.
Application 18/299,452 is a continuation of application No. 17/470,682, filed on Sep. 9, 2021, granted, now 11,645,084.
Application 17/470,682 is a continuation of application No. 16/686,060, filed on Nov. 15, 2019, granted, now 11,126,439, issued on Sep. 21, 2021.
Prior Publication US 2023/0325196 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/3887 (2013.01) [G06F 9/30098 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a graphics processor that includes:
first storage circuitry configured to store multiple thread-specific versions of a first register for a threads of a single-instruction multiple-data (SIMD) group;
second storage circuitry configured to store multiple thread-specific versions of a second register for the threads of the SIMD group;
third storage circuitry configured to store multiple thread-specific versions of a third register for threads of the SIMD group; and
a set of multiple hardware pipelines configured to:
execute, using routing circuitry, an instruction to:
store a proper subset of the thread-specific versions of the first register from the first storage circuitry in thread-specific versions of the third register in the third storage circuitry; and
store a proper subset of the thread-specific versions of the second register from the second storage circuitry in thread-specific versions of the third register in the third storage circuitry;
wherein the storage of the proper subsets stores values that are based on thread-specific versions of the first and second registers to other threads' versions of the third register for the SIMD group.