US 12,008,369 B1
Load instruction fusion
John D. Pape, Cedar Park, TX (US); Skanda K. Srinivasa, Austin, TX (US); Francesco Spadini, Sunset Valley, TX (US); and Brian T. Mokrzycki, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 25, 2022, as Appl. No. 17/652,501.
Application 17/652,501 is a continuation of application No. 17/463,321, filed on Aug. 31, 2021, abandoned.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30058 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/3838 (2013.01); G06F 9/3858 (2023.08); G06F 9/3861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A hardware processor, comprising:
a load/store circuit;
a branch execution circuit coupled to the load/store circuit; and
a decoder circuit coupled to the load/store circuit and configured to:
detect a first instruction to load a first value from a memory;
detect a conditional branch instruction that depends on the first value to be loaded by the first instruction; and
fuse the first instruction and the conditional branch instruction such that one or more operations that the conditional branch instruction is defined to perform are to be executed within the load/store circuit;
wherein the load/store circuit is configured to:
receive a first indication of the fused first instruction and conditional branch instruction; and
load the first value from the memory;
detect whether the first value satisfies a condition of the conditional branch instruction; and
provide a second indication to the branch execution circuit on whether the condition has been satisfied; and
wherein the branch execution circuit is configured to:
access information about the conditional branch instruction;
determine the condition of the conditional branch instruction; and
provide a third indication of the condition to the load/store circuit to enable the load/store circuit to detect whether the first value satisfies the condition.