US 12,008,367 B2
Systems and methods for performing 16-bit floating-point vector dot product instructions
Alexander F. Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Raanan Sade, Kibutz Sarid (IL); Menachem Adelman, Haifa (IL); Zeev Sperber, Zichron Yackov (IL); Amit Gradstein, Binyamina (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 21, 2022, as Appl. No. 17/845,103.
Application 17/845,103 is a continuation of application No. 16/186,378, filed on Nov. 9, 2018, granted, now 11,366,663, issued on Jun. 21, 2022.
Prior Publication US 2022/0326949 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3016 (2013.01); G06F 9/3802 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A processor comprising:
fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of elements of the specified first and second sources having a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, and accumulate resulting products with previous contents of a corresponding element of the specified destination;
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode.