US 12,008,303 B2
Cell overlap violation diagnostics with machine learning
Leslie K. Hwang, Chandler, AZ (US); and Srinivasa R. Arikati, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,876.
Claims priority of provisional application 63/072,069, filed on Aug. 28, 2020.
Prior Publication US 2022/0067265 A1, Mar. 3, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design, the method comprising:
receiving an IC chip design layout;
performing a DRC process on the IC chip design layout to identify DRC violations;
generating heatmaps for the DRC violations, wherein each of the DRC violations corresponds to a different one of the heatmaps;
generating, by one or more processors, clustered heatmaps from the heatmaps generated for the DRC violations by combining two or more of the heatmaps that are associated with a first error within the IC chip design layout; and
identifying, by the one or more processors, a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.