US 12,008,302 B2
Integrated circuit with thicker metal lines on lower metallization layer
Kuang-Hung Chang, Hsinchu (TW); Yuan-Te Hou, Hsinchu (TW); Chung-Hsing Wang, Hsinchu County (TW); and Yung-Chin Hou, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 23, 2023, as Appl. No. 18/173,731.
Application 18/173,731 is a continuation of application No. 17/404,511, filed on Aug. 17, 2021, granted, now 11,593,546.
Application 17/404,511 is a continuation of application No. 16/900,684, filed on Jun. 12, 2020, granted, now 11,113,443, issued on Sep. 7, 2021.
Prior Publication US 2023/0205966 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 27/00 (2006.01); H01L 27/088 (2006.01)
CPC G06F 30/392 (2020.01) [G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01); H01L 23/528 (2013.01); H01L 27/0886 (2013.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
a first net electrically connecting the first transistor and the second transistor, the first net comprising a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors; and
a second net electrically connecting the third transistor and the fourth transistor, the second net comprising a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors, wherein a count of the plurality of first metal vias of the first net is less than a count of the plurality of second metal vias of the second net, and a line height of each of the plurality of first metal lines of the first net is greater than a line height of each of the plurality of second metal lines of the second net.