CPC G06F 30/392 (2020.01) [G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01); H01L 23/528 (2013.01); H01L 27/0886 (2013.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] | 20 Claims |
1. An integrated circuit (IC) structure, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate;
a first net electrically connecting the first transistor and the second transistor, the first net comprising a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors; and
a second net electrically connecting the third transistor and the fourth transistor, the second net comprising a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors, wherein a count of the plurality of first metal vias of the first net is less than a count of the plurality of second metal vias of the second net, and a line height of each of the plurality of first metal lines of the first net is greater than a line height of each of the plurality of second metal lines of the second net.
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